The present invention relates to a semiconductor device comprising a high conductivity interconnect structure, and to a method of forming the high conductivity interconnect structure. The present invention is applicable to high speed integrated circuits, particularly integrated circuits having sub-micron design features.
As integrated circuit geometry continues to plunge into the deep sub-micron regime, it becomes increasingly difficult to satisfy the requirements of high performance microprocessor applications for rapid circuitry speed. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction of design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Copper (Cu) is considered a viable alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Cu has a lower bulk resistivity and potentially higher electromigration tolerance than Al. Both the lower bulk resistivity and higher electromigration tolerance improve circuit performance. A conventional approach to forming a Cu interconnection involves the use of damascene processing in which openings are formed in an interlayer dielectric (ILD) and then filled with Cu. Such damascene techniques typically include single as well as dual damascene techniques, the latter comprising forming a via opening in communication with a trench opening and simultaneously filling by metal deposition to form a via in communication with a metal line.
However, Cu is a mid-gap impurity in silicon and silicon dioxide. Accordingly, Cu diffusion through interlayer dielectrics, such as silicon dioxide, degrades the performance of the integrated circuit. A conventional approach to the diffusion problem comprises depositing a barrier material to encapsulate the Cu line. Typically diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between the Cu and the ILD, but includes interfaces with other metals as well. In depositing Cu by electroless deposition or electroplating, a seedlayer is also typically deposited to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seedlayer must be continuous. However, for electroless plating, very thin catalytic layers can be employed in the form of eyelets.
Conventional damascene interconnect methodology involving metal deposition, including Cu deposition, typically comprises depositing a layer of metal, e.g., barrier metal/seedlayer/Cu, annealing, as at about 100xc2x0 C. to about 450xc2x0 C. for Cu, and then planarizing, as by chemical-mechanical polishing (CMP), such that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. A capping layer, such as silicon nitride, is then typically deposited to complete encapsulation of Cu inlaid metallization.
During such conventional damascene methodology the annealing step is conducted to relieve stress within the filled opening generated by damascene filling. However, it was found that voiding typically occurs within the filled openings, e.g., metal lines, leading to electromigration failure.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices comprising interconnect patterns with reduced voids and reduced electromigration failures. There exists a particular need for methodology enabling the fabrication of semiconductor devices comprising Cu interconnection patterns semiconductor devices having metal levels with varying line widths in the deep sub-micron regime.
An advantage of the present invention is a method of manufacturing a semiconductor device containing metallized interconnection patterns, particular Cu interconnection patterns, with lines having improved electromigration resistance and substantially no or significantly reduced voids.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a plurality of openings in a dielectric layer; depositing a layer of metal partially filling the openings; annealing to effect grain growth of the metal deposited within the openings; and depositing a layer of metal to completely fill the openings.
Embodiments of the present invention comprise forming a plurality of trenches in an ILD, depositing a layer of Cu or a Cu alloy partially filling the openings, leaving sufficient empty space within the openings to prevent the generation of voids upon subsequent annealing to effect grain growth of the Cu or Cu alloy within the partially filled trenches, and annealing at a temperature, as at about 100xc2x0 C. to about 450xc2x0 C., in a suitable atmosphere, such as nitrogen or a forming gas comprising nitrogen and hydrogen, to effect grain growth of the Cu or Cu alloy within the partially filled trenches. Subsequently, Cu or a Cu alloy, is deposited to completely fill the trenches and a second annealing is conducted under substantially the same conditions as the first annealing of the partially filled trenches. Subsequently, CMP is conducted to effect planarization so that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. A capping layer, such as silicon nitride, is then deposited to encapsulate the Cu or Cu alloy lines within the trenches. Embodiments include depositing a Cu or Cu alloy to fill about 70% to about 90% of the volume of the trenches before conducting the first annealing.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.